The semiconductor industry continues to decrease the minimum feature-size of transistors and thereby increase the density of transistors on an integrated circuit (IC). Today, billion-transistor circuits are being produced and much higher densities are forecast for the years to come. However, it has become increasingly difficult to meet timing constraints throughout an integrated circuit that has but a single clock domain. A globally-asynchronous, locally-synchronous (GALS) approach has been gaining in popularity to overcome this difficult architectural problem. The GALS approach is to partition a system design into decoupled clock-independent modules that can be designed to meet their individual requirements. These independent modules can then be coupled using an asynchronous interconnect network or an asynchronous network-on-chip (ANoC), which improves reliability by simplifying clock-domain crossing timing by using delay-tolerant connection modules. However, the complexity of such interconnect networks (measured in terms of the number of different ways control signals traverse such an interconnect network) grows exponentially instead of linearly as the number of independent control network elements used in implementing the interconnect network is increased. Therefore, providing a reliable interconnect network becomes problematic without a methodology to control this increased complexity.